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Sequential logic testing and verification

by Abhijit Ghosh, Srinivas Devadas, A. Richard Newton. -- Kluwer Academic, 1992. -- (The Kluwer international series in engineering and computer science ; SECS 163 . VLSI, computer architecture and digital signal processing). <BB00433264>
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Sequential logic testing and verification

by Abhijit Ghosh, Srinivas Devadas, A. Richard Newton. -- Kluwer Academic, 1992. -- (The Kluwer international series in engineering and computer science ; SECS 163 . VLSI, computer architecture and digital signal processing). <BB00433264>
Tag:
No tag is registered
Functions:
Contents and Summary Details
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No. Volumes Location Section Material format Call No Material ID Status Due Date Reservation
0001 : alk. paper B2：2nd basement 549.92||GHO 00637674 0items
No. 0001
Volumes : alk. paper
Location B2：2nd basement
Section
Material format
Call No 549.92||GHO
Material ID 00637674
Status
Due Date
Reservation 0items
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Bibliography Details

title and statement of responsibility area Sequential logic testing and verification / by Abhijit Ghosh, Srinivas Devadas, A. Richard Newton
publication,distribution,etc.,area Boston : Kluwer Academic , c1992
physical description area xv, 214 p. : ill. ; 25 cm
Volume Information
ISBN 0792391888
parent bibliography link The Kluwer international series in engineering and computer science <BB00753842> SECS 163 . VLSI, computer architecture and digital signal processing//aa
note Includes bibliographical references (p. 199-211) and index
NCID BA13630708
text language code English
author link *Ghosh, Abhijit, 1964- <AU00246022>
author link Devadas, Srinivas <AU00136767>
author link Newton, A. Richard (Arthur Richard), 1951- <AU00187452>
classification LCC:TK7868.L6
classification DC20:621.39/5
subject headings Logic circuits -- Testing
subject headings Logic design
subject headings Computer-aided design
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